In today's electronic packages, many packages are fabricated as composites of material. In other words, the packages include a combination of various materials that are layered together to form an end product. During manufacturing, assembly, and operation, temperature changes in each material can generate internal stresses therein due to the different mechanical properties of each material. For example, the coefficient of thermal expansion can be different for each material that forms an electronic package, and the thermal mismatch between materials can result in cracking, warpage, etc.
Warpage presents significant design concerns when fabricating an electronic package. The design challenges include surface mount technology yield issues, capability for reduction of solder ball pitch, solder ball stress, and board level reliability. Great effort continues to be put forth towards reducing and/or eliminating warpage in electronic packaging. However, most of these efforts are focused on reducing warpage at the strip level (i.e., before cutting or dicing the packages into singulated, unitary packages). In spite of these efforts, there continue to be concerns and problems with warpage in conventional electronic packaging.
Therefore, it would be desirable to develop an electronic package and method of manufacturing the package which could be designed to compensate for warpage. In particular, it would be desirable to reduce the effects of warpage on a singulated, unitary electronic package.